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ASE details panel-level packaging for AMD Venice CPU, targeting Q1 2027

1 article1 sourcesince Oct 28Last article 2h ago · Oct 28, 3:34 PM ET

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ASE showed its panel-level packaging solution for AMD's Venice CPU, with initial production targeted for Q1 2027 at limited scale at its Kaohsiung facility, according to SemiAnalysis.

ASE and its subsidiary SPIL implemented the second generation of their Fan-Out Embedded Bridge (FOEB) technology in Venice.

SemiAnalysis reports that a 310 × 310 mm panel fits 25 Venice interposers after edge loss, compared with 22 on a traditional round 300 mm carrier wafer, a roughly 14% increase in gross package count.

Written by AI from the articles below · updated Oct 28, 3:44 PM ET

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Latest developmentOct 28, 3:34 PM ET

ASE details panel-level packaging for AMD Venice CPU, targeting Q1 2027

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Oct 28

3:34 PM
SemiAnalysis@SemiAnalysis_X
ASE details panel-level packaging for AMD Venice CPU, targeting Q1 2027
AIASE showed its panel-level packaging solution for AMD's Venice CPU, with initial production targeted for Q1 2027 at limited scale at its Kaohsiung facility. ASE and subsidiary SPIL implemented the second generation of their Fan-Out Embedded Bridge (FOEB) technology in Venice. A 310 × 310 mm panel fits 25 Venice interposers after edge loss, versus 22 on a round 300 mm wafer, about 14% more packages per carrier.

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