ASE details panel-level packaging for AMD Venice CPU, targeting Q1 2027

ASE showcased its panel-level packaging (PLP) solution for AMD’s Venice CPU, with initial production targeted for Q1 2027, likely at limited scale at its Kaohsiung facility. ASE and its subsidiary SPIL have worked with AMD to implement the second generation of their Fan-Out Embedded Bridge (FOEB) technology in Venice. The current 310 × 310 mm panel accommodates 25 Venice interposers after edge loss, compared with 22 on a traditional round 300 mm carrier wafer, roughly a 14% increase in gross package count. This modest improvement in package output per carrier represents a starting point for panel-level interposers with Venice’s 2.7x reticle size, rather than evidence of a dramatic reduction in cost. (1/2)🧵
Source: OCP ASE Booth