Nvidia Vera server chip reaches 1.228 TB/s memory bandwidth, Chips and Cheese reports
Overview
Chips and Cheese reports that Nvidia's Vera server chip can move up to 1.228 TB/s of memory bandwidth through its Memory Switch Nodes, which bridge to a 1024-bit LPDDR5X-9600 interface.
The report says memory latency stays under 200 ns even under heavy bandwidth load.
The chip uses a second-generation Scalable Coherency Fabric, with Coherency Switch Nodes hosting pairs of Olympus cores. Chips and Cheese also measures Vera's 164 MB shared L3 cache at about 3.35 TB/s of read bandwidth, or 33.1 GB/s per core.
Written by AI from the articles below · updated Oct 19, 2:39 PM ET
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- Chips and CheeseBlogNvidia Vera's system architecture pushes memory bandwidth to 1.228 TB/s
AINvidia's Vera server chip uses a second-generation Scalable Coherency Fabric, with Coherency Switch Nodes hosting pairs of Olympus cores and Memory Switch Nodes bridging to a 1024-bit LPDDR5X-9600 interface. The MSNs can move up to 1.228 TB/s of memory bandwidth, and Vera's memory latency stays under 200 ns even under heavy bandwidth load. Vera's 164 MB shared L3 cache delivers about 3.35 TB/s of read bandwidth, or 33.1 GB/s per core.
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