Nvidia Vera's system architecture pushes memory bandwidth to 1.228 TB/s

Nvidia's Vera server chip uses a second-generation Scalable Coherency Fabric, with Coherency Switch Nodes hosting pairs of Olympus cores and Memory Switch Nodes bridging to a 1024-bit LPDDR5X-9600 interface.

The MSNs can move up to 1.228 TB/s of memory bandwidth, and Vera's memory latency stays under 200 ns even under heavy bandwidth load. Vera's 164 MB shared L3 cache delivers about 3.35 TB/s of read bandwidth, or 33.1 GB/s per core.