Qualcomm validates first-generation HBC silicon for Dragonfly AI250 accelerator
Overview
Qualcomm says its first-generation high-bandwidth computing (HBC) silicon is now validated in its lab, with the full memory read-write path and near-memory computations tested at production levels.
The architecture places an AI accelerator under a stack of LPDDR memory, and Qualcomm says it will be integrated into the Dragonfly AI250.
Qualcomm claims the design delivers up to 18 times the memory bandwidth of LPDDR and five times the TB/s-per-watt energy efficiency of HBM4. The Next Platform reports these figures from Qualcomm's statements; they are the company's claims, not independent measurements.
Qualcomm expects the AI250 to begin sampling in the first half of 2027. The HBC validation is the first step in a multi-year roadmap that also includes the Dragonfly C1000 CPUs, due to sample next year, and the Dragonfly AI300, due to sample in 2028.
Written by AI from the articles below · updated Nov 2, 1:05 PM ET
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- The Next PlatformNewsQualcomm says its HBC near-memory architecture cuts AI inference memory bandwidth gap
AIQualcomm says its first-generation high-bandwidth computing (HBC) silicon, now validated in its lab, delivers up to 18 times the memory bandwidth of LPDDR and five times the TB/s-per-watt energy efficiency of HBM4. The architecture places an AI accelerator under a stack of LPDDR memory and will be integrated into the Dragonfly AI250, which Qualcomm expects to sample in the first half of 2027.
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