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TSMC to present A14 6T SRAM bitcell under 0.017 µm² at IEDM

1 article1 sourcesince Oct 20Last article 1h ago ·

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TSMC will present a 6T High Density SRAM bitcell under 0.017 µm² on its A14 process at IEDM, according to SemiAnalysis.

The cell is slated for 2028 and is about 25% denser than the 0.021 µm² bitcell TSMC has used since its N5 process in 2020.

SemiAnalysis describes the cell as the world's smallest 6T High Density SRAM bitcell.

Written by AI from the articles below · updated Oct 20, 9:28 PM ET

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Latest developmentOct 20, 9:06 PM ET
TSMC shrinks 6T SRAM bitcell to under 0.017μm² for A14

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Oct 20
  1. SemiAnalysisX
    TSMC shrinks 6T SRAM bitcell to under 0.017μm² for A14

    AITSMC will present at IEDM the world's smallest 6T High Density SRAM bitcell, under 0.017μm², on its A14 process, slated for 2028. The new cell is about 25% denser than the 0.021μm² bitcell TSMC has used since N5 in 2020.

    Image from @SemiAnalysis_'s post

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