After eight long years, TSMC is finally shrinking their 6T High Density SRAM bitcell for their A14 process! At IEDM, they will present the world's smallest bitcell, <0.017μm2 on their 2028 node. TSMC has been stuck at 0.021μm2 since N5 in 2020. With designs utilizing even more SRAM as memory bottlenecks grow, a 25% denser SRAM with A14 is significant.
TSMC shrinks 6T SRAM bitcell to under 0.017μm² for A14
AITSMC will present at IEDM the world's smallest 6T High Density SRAM bitcell, under 0.017μm², on its A14 process, slated for 2028. The new cell is about 25% denser than the 0.021μm² bitcell TSMC has used since N5 in 2020.
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SemiAnalysis · x.comPublished · added here
Original title: After eight long years, TSMC is finally shrinking their 6T High Density SRAM bitcell for their A14 process! At IEDM, they will present th...