Archgen plans to tape out its first 3D-stacked chip in April 2027

AIArchgen, a Y Combinator startup, is designing chips that stack transistors in layers to shorten signal paths and reduce power. The company says its thermal model predicts chip temperature about 5,000 times faster than standard design software and claims up to 40% less power for the same work.

Rohan Paul

@rohanpaul_ai

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Chips have mostly improved by shrinking transistors, and that is getting very hard.

so YC startup @archgen_ is designing chips that stack transistors in layers like a skyscraper, letting signals travel shorter distances and use less power.

Stacking chip layers is possible, but the stack traps heat, so Archgen built an AI model that predicts chip temperature about 5,000x faster than standard chip design software.
i.e. it will let engineers find hot spots while they design.

And shorter wires carry less capacitance, so every switch costs less energy and settles faster. Archgen’s figure is up to 40% less power for the same work.

hari_haran (building archgen YC F26)@HariAyapps

@archgen_ is building skyscrapers for semiconductor chips Shrinking transistors is getting harder. Stacking them makes heat harder to manage. We’re building the tools to design chips in three dimensions. We stack transistors vertically, shorten connections, and optimize timing and heat together. Our foundational model for thermal simulation, predicts temperature roughly 5,000× faster than conventional EDA tools. Our placement engine ranked #1 in HRT’s macro-placement challenge We’re working with some of the largest fabs in the world to tape out our first chip in April 2027 http://archgenlabs.com

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Rohan Paul · x.comPublished Nov 9, 3:09 PM ET · added here 9:21 PM ET

Original title: Chips have mostly improved by shrinking transistors, and that is getting very hard.

Archgen plans to tape out its first 3D-stacked chip in April 2027

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