Every solid-state quantum pitch deck claims manufacturing is solved because it uses standard CMOS foundries.
Then you listen to the people who run those fabs talk about their KPIs 😅
I talk about wafer economics, cryo testing, PDKs, and 35+ fabs 👀 https://x.com/i/article/2117306172651024384
Why Classical Semiconductor Fabs Secretly Hate Quantum Chips
Originally published on Quantum Capital on Substack. Read the full essay here.
A common quantum computing talk point for certain modalities: "Because we use standard semiconductor fabrication, manufacturing is already solved."
In Is It Too Early to Scale Quantum?, I wrote about how the industry's favorite talking point has shifted from qubit counts and fidelities to foundry partnerships. So when I was at the Global Quantum Industry Group (GQIG) Quantum Infra Summit EU 2026 at imec in Leuven in October 2026, one of my favorite sessions was the foundry panel.
Moderator Oreste Donzella (an Advisory Board Member of the International Semiconductor Industry Group with 33 years across Texas Instruments, Micron, and KLA) sat down with three people bridging commercial fabs and quantum hardware.
On stage alongside Oreste Donzella were:
Dr. Mihir Bhaskar (SVP and GM of SkyWater Quantum Solutions at SkyWater Technology),
Dr. Nicholas Sergeant (VP Quantum Technology Solutions at GlobalFoundries),
and Richard Kuncic (SVP and GM at Infineon Technologies).
Right at the start, both sides admitted how wide the gap still is in conversation between the two industries. Donzella joked that after 33 years in semiconductors, he knew nothing about quantum until three weeks before the panel, and the semiconductor industry barely knows more. Bhaskar said the opposite. He came from quantum R&D.
Here’s what I took away from the panel: four places where what quantum startups need is the exact opposite of how classical semiconductor fabs make money.
1. Every metric a fab manager cares about doesn’t work for quantum right now
Donzella asked about KPIs: with quantum wafer volumes still measured in dozens and the processes that are pretty experimental, what is the return on investment of letting quantum into your process?
Richard Kuncic from Infineon explained that beyond counting R&D spend, the real investment is allowing that kind of disturbance inside a production fab:
"What we do in quantum is not supporting any of the KPIs for those who run the fab. It's not helping with the throughput. It's not helping with the cost per wafer or manufactured layer. It goes against all their native interests, and therefore you need this strategic conviction to go for that."
How does a classical semiconductor fab operate? A commercial foundry spends billions equipping a line. It makes money running tens of thousands of identical wafers around the clock through a frozen process flow, backed by a standardized Process Design Kit (PDK) of design rules and device models.
Quantum disrupts that in three ways:
- Materials and contamination rules: Classical CMOS lines have strict contamination controls because a few stray metal atoms can ruin everything. Superconducting and trapped-ion teams ask to deposit niobium, tantalum, aluminum, or gold, or to run custom surface treatments and undercut etches that CMOS lines never allow. (Silicon spin qubits stick to CMOS-compatible transistor materials, though high-coherence spin devices still need custom starting wafers with isotopically purified silicon-28 layers.)
- Frozen flows vs. recipe changes (and how AI chip startups tape out): A fab's "process recipe" is the exact sequence the tools run (which acids clean the silicon, how many nanometers get deposited, and which gases etch the trenches). Classical AI chip startups don't order millions of wafers on day one either, yet they can run on TSMC's 3nm line because they never touch TSMC's recipe. Working with an ASIC partner like Broadcom, an AI startup designs inside TSMC's frozen PDK. Electronic Design Automation (EDA) tools from Synopsys and Cadence model transistor behavior well enough to yield working silicon on the first pass (some of the time - respins are still common but no fault of the fab, more on the design). Quantum teams are usually still tweaking specs.
- Photomask economics and demand: Even when the recipe stays fixed, every chip layer is printed through a custom quartz stencil called a photomask (or reticle). A full mask set costs roughly $1 million to $3 million at 90nm to 45nm and an estimated $15 million to $40 million at 3nm. Classical chips need new masks when bugs slip through too, but simulation catches most bugs early and AI chip vendors amortize masks across millions of dies. Quantum volumes look completely different. IBM has deployed over 90 quantum systems globally, and IQM reported 17 full systems delivered out of 26 sold in its August 2026 half-year update. QED-C's 2026 Market Forecast puts the entire 2025 quantum computing market at $1.4 billion. When you only get a dozen working chips per hardware generation, a production mask set cost is high per chip. That's why foundries are testing maskless tools like Multibeam's multicolumn e-beam system (SkyWater received the first production unit), writing patterns directly with electron beams instead of masks.
2. Paying for engineers, not wafers
If quantum wafers hurt traditional fab KPIs, how does a foundry justify taking the work?
SkyWater is a great case study here, especially after IonQ closed its acquisition of SkyWater in July 2026 at an announced value of $1.8 billion, making SkyWater a wholly owned IonQ subsidiary. SkyWater has operated for years as what Bhaskar noted CEO Tom Sonderman calls a "technology foundry," selling Technology as a Service rather than just running volume PDKs. When Donzella pressed Bhaskar on how SkyWater makes the math work for its board, Bhaskar described the model they rely on:
"Especially since SkyWater was purchased by IonQ, the whole company lives and dies with the success of the quantum industry and all of our quantum customers... You need a certain amount of volume running through the foundry to keep it healthy and stable, and that helps to offset some of the fixed costs. The quantum work is engineering services. It's different economics around it. You think of it as dollars per engineer and not so much dollars per wafer, and you have to build a business model where those two things can add up and become profitable."
Bhaskar also shared a revenue breakdown showing why most quantum budgets stay stuck in wafer development rather than advanced packaging. In classical AI chips (like Nvidia's Blackwell), individual compute dies already yield well, so the foundry bottleneck has shifted to advanced packaging: stitching compute dies and HBM together. They’re selling systems. When Donzella asked why foundry packaging barely came up over the summit, Bhaskar pointed to where SkyWater's quantum revenue comes from:
"We have two primary facilities where we do work that's relevant to quantum. One is in Minnesota, which is the wafer fab, and one is in Florida, our 200-millimeter and 300-millimeter advanced packaging fab. And to give you a sense, I would say about 90% of revenue in dollars drives right now from Minnesota, and 10% from Florida. And I think it's natural because a lot of people, where they are in the roadmap today, are still trying to make the die work, right? And once you're still iterating on getting a good die by running many wafers and doing the process control, you're probably not going to be also looking to a foundry to do the advanced packaging and connecting chiplets. You're just not there yet."
Packaging quantum together makes no sense until you can fabricate one working quantum die at high yield. The one exception, Bhaskar noted, is photonic quantum computing: silicon and silicon nitride lack nonlinear optical properties, so photonic teams must heterogeneously integrate from day one. For almost everyone else in solid-state quantum, 90% of foundry spend goes into the wafer fab just trying to make one die work.
3. Room-temperature fab tests don't predict cold qubits
Even after a wafer comes off the line, two technical problems separate classical semiconductor yield from quantum yield.
The first is how you handle defects. As I wrote in The Quantum Supply Chain Isn't Venture-Backable, semiconductor engineers once explained CPU "binning" to me (if two cores on an eight-core die fail, you disable them and sell the chip as an i5 instead of an i7). I told them they couldn't make fun of our quantum chips anymore.
In quantum, as Infineon's Kuncic explained:
"In typical semiconductor manufacturing, you focus on the mean distribution and the variation of the parameters, and in quantum computing, sometimes it's also the tail end that matters. That needs really special approaches that we also use, for example, in automotive for zero defect, to address this because that does matter when you try to have a large system."
Qubits are delicate analog devices, and a few bad qubits make the whole chip much harder to use. You can compile around isolated defects or deform an error-correcting code around a dead qubit, at a cost. In Q-CTRL's Fermi-Hubbard demonstration on IBM's 156-qubit Heron processor, only 21 of 108,988 possible 120-qubit chain layouts avoided the chip's three persistently high-noise qubits. If too many qubits fail, you run out of layouts altogether. For the past decade, academic papers dodged this by reporting "hero devices": fabricating dozens of chips and publishing the single best device on the bell curve. That is why Diraq and imec's 2025 Nature study on 300mm CMOS spin qubits was something new. Rather than cherry-picking one hero chip, they measured four randomly selected devices from a 300mm wafer.
The second problem is how long it takes to find out a process step drifted. A commercial CMOS wafer runs through 500 to over 1,000 steps across three to four months. Inside a classical fab, the feedback loop is much faster because automated optical and e-beam tools check film thickness, line width, overlay, and etch depth inline. If step 30 drifts out of spec, the fab catches it that afternoon. Engineers rework the layer or scrap the wafer before wasting three months on a dead lot.
In quantum, as GlobalFoundries' Nicholas Sergeant pointed out, room-temperature inline tests don't always correlate with how qubits behave near absolute zero.
Worse, as Bhaskar admitted on stage, the quantum industry hasn't run enough wafers yet to build the statistical correlation tables that would let a fab catch quantum defects inline:
"I don't think we've even generated the dataset that is of a sufficient size that's comparable to what we think of in the semiconductor industry when we're actually doing process control... You may be able to correlate your room temperature or your 4K wafer-scale electrical properties with the performance that you see. We just don't even have the level of statistics that you would need on the quantum properties. So it will take a few years, I think, to be able to build up those correlations."
In classical CMOS, statistical process control rests on millions of data points from room-temperature wafer probers testing thousands of dies per hour. Commercial automated cryogenic wafer probers typically reach 1 to 4 Kelvin right now. (Sub-100 millikelvin wafer-scale probers from Bluefors and JPE and sub-50 millikelvin socketed systems from FormFactor are starting to appear.) That 1 to 4 Kelvin regime is cold enough to probe "hot" silicon spin qubits around 1 Kelvin. Superconducting qubits at 10 to 20 millikelvins (and spin qubits at millikelvin operating points) still mostly cool down a few chips at a time in a dilution refrigerator. Earlier at the summit, Vishal Chatrath, Co-Founder and CEO of QuantrolOx, put numbers on that gap. Building a real semiconductor PDK requires characterizing tens of thousands of samples a year. Meanwhile, a team of quantum PhDs can spend months characterizing one 50-qubit chip across lab instruments that don't share a common data format.
4. Why you can't just copy-paste a recipe between cleanrooms and foundries
What about the dozens of startups currently building their first prototypes in university cleanrooms, planning to transfer their recipe later?
During the audience Q&A, someone asked how technologies developed on European pilot lines transition into commercial foundries.
Sergeant's answer from GlobalFoundries:
"At some point that transition has to happen, and that transition can take time as well. And in some cases, there is a real need to redesign and restart and redevelop the process flow from scratch, bottom up, because those transitions are sometimes really difficult."
In classical AI silicon, startups don't have to become foundry-transfer experts because an entire middle layer handles it for them. When OpenAI designed its Jalapeño inference chip, they went straight to Broadcom. Custom AI silicon is now a massive business (Broadcom's AI semiconductor revenue hit $16.7 billion in Q3 FY2026 alone). In a typical custom ASIC flow, the startup writes the high-level architecture, and Broadcom drops in pre-verified networking and HBM memory IP blocks. Then Broadcom translates the design into a foundry PDK like TSMC's, manages packaging, and ships back tested chips (and don’t even get me started on how we need to store the quantum chips to keep them working. that’s another story).
Who actually pays to turn a science project into a foundry process?
In the 1960s and 1970s, as Chris Miller chronicles in Chip War, every chip company was an integrated device manufacturer like Fairchild, Intel, or AMD. Transistor physics, fab recipes, and circuit layouts were completely entangled. Designing a chip meant building your own cleanroom and tuning diffusion furnaces yourself (and when fabless startups appeared, AMD founder Jerry Sanders famously scoffed that "Real men have fabs").
What broke this bottleneck?
First, in 1980, Caltech physicist Carver Mead and Xerox PARC computer scientist Lynn Conway published Introduction to VLSI Systems, separating chip design from wafer fabrication with geometric design rules. In 1981, DARPA launched the MOSIS shuttle service so universities and startups could share wafer runs without owning a fab.
Second, in the 1980s, EDA companies like Cadence and Synopsys turned those design rules and transistor models into software simulators, so engineers could verify a chip on a workstation before taping out silicon.
Third, in 1987, Morris Chang founded TSMC (backed by Taiwan's government and Philips) on one rule: TSMC would never design its own chips or compete with customers, locking down high-volume processes behind standardized PDKs.
Standardized design rules, predictive EDA software, and a neutral pure-play foundry ended the era where every chip startup had to be a manufacturing company. That stack is what let fabless giants like Nvidia, Qualcomm, and Broadcom exist.
So if standard TSMC-style CMOS lines won't touch custom quantum recipes, where do quantum chips actually get made?
Below, I map out the five models for where quantum processors and components actually get printed, from SkyWater, Anderon, GlobalFoundries, and Infineon to QuantWare, U.S. national labs, European pilot lines, and university cleanrooms. Here’s what each facility can and can't run.
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