Google reworks TPU 8 accelerators for inference with new 8tx and 8i Max variants
AIGoogle plans two TPU 8 variants for 2027 rollout: the TPU 8tx, aimed at inference, and the TPU 8i Max, which pairs two chips for larger context workloads. The 8tx swaps the 3D torus interconnect for a boardfly design, cutting pod size from 9,600 to 1,152 accelerators, while the 8i Max halves per-chip HBM capacity to 192 GB. The author notes that Google's TPU Sync software, which moves working memory off chip during agent pauses, is designed to raise utilization and lower cost per agentic workload.
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The article explains how Google reconfigures its TPU 8 designs for inference, shifting interconnect, CPU, and memory tradeoffs, which clarifies cost and capacity decisions behind agentic AI workloads.
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The Next Platform · nextplatform.comPublished · added here
Original title: Google Rejiggers TPU Accelerators For Broader AI Inference Work