# Archgen plans to tape out its first 3D-stacked chip in April 2027

> Original title: Chips have mostly improved by shrinking transistors, and that is getting very hard.

- Source: Rohan Paul
- Published: 2026-11-09T20:09:24.000Z
- Bad Influence: https://badinfluence.news/items/lp9d0mzlyra44iy3h5jljqzu3
- Original: https://x.com/rohanpaul_ai/status/2119885084610470314

## Summary

Archgen, a Y Combinator startup, is designing chips that stack transistors in layers to shorten signal paths and reduce power. The company says its thermal model predicts chip temperature about 5,000 times faster than standard design software and claims up to 40% less power for the same work. Archgen says it is working with large fabs to tape out its first chip in April 2027.

## Post

Chips have mostly improved by shrinking transistors, and that is getting very hard. 

so YC startup @archgen_ is designing chips that stack transistors in layers like a skyscraper, letting signals travel shorter distances and use less power.

Stacking chip layers is possible, but the stack traps heat, so Archgen built an AI model that predicts chip temperature about 5,000x faster than standard chip design software. 
i.e. it will let engineers find hot spots while they design.

And shorter wires carry less capacitance, so every switch costs less energy and settles faster. Archgen’s figure is up to 40% less power for the same work.

[Video](https://badinfluence.news/api/img-proxy?u=https%3A%2F%2Fpbs.twimg.com%2Famplify_video_thumb%2F2119884612650532864%2Fimg%2FdBysEmz5JbJXTZam.jpg&mode=thumb&exp=1794528000&sig=718f1e13fb9cc470)

## Quoted post @HariAyapps

> @archgen_ is  building skyscrapers for semiconductor chips
> 
> Shrinking transistors is getting harder. Stacking them makes heat harder to manage. We’re building the tools to design chips in three dimensions.
> 
> We stack transistors vertically, shorten connections, and optimize timing and heat together.
> 
> Our foundational model for thermal simulation, predicts temperature roughly 5,000× faster than conventional EDA tools.
> 
> Our placement engine ranked #1 in HRT’s macro-placement challenge
> 
> We’re working with some of the largest fabs in the world to tape out our first chip in April 2027
> 
> http://archgenlabs.com

https://x.com/HariAyapps/status/2119839344836145361